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1 pf979-02 E0C63P466 4-bit single chip microcomputer n description the E0C63P466 is a cmos 4-bit microcomputer composed of a 4-bit cmos core cpu, rewritable rom (flash), ram, dot-matrix type lcd driver, serial interface and timers. the E0C63P466 has a built-in large- capacity flash rom (16k 13 bits) and a ram (5k 4 bits), and is upper compatible with the e0c63454, e0c63458 and e0c63466. the E0C63P466 can be used as a mtp (multi-time programming) when develop- ing programs. n features l cmos lsi 4-bit parallel processing ..... e0c63000 core cpu l osc1 oscillation circuit ......................... 32.768khz (typ.) crystal oscillation l osc3 oscillation circuit ......................... 4mhz (typ.) ceramic oscillation l instruction set ........................................ basic instruction : 46 types (411 instructions with all) addressing mode : 8 types l instruction execution time ..................... during operation at 32.768khz : 61sec, 122sec, 183sec during operation at 4mhz : 0.5sec, 1sec, 1.5sec l rom (flash) capacity ........................... code rom : 16,384 words 13 bits data rom : 2,048 words 4 bits (8k bits) programming : parallel and serial programming (exclusive rom writer is used) rewriting : 10 times l ram capacity ........................................ data memory : 5,120 words 4 bits display memory : 1,020 bits (240 words 4 bits + 60 1 bit) l input port ............................................... 8 bits (with pull-up resistors) l output port ............................................ 12 bits (it is possible to switch the 2 bits to special output * 1) l i/o port .................................................. 12 bits (it is possible to switch the 2 bits to special output and the 4 bits to serial i/f input/output * 1) l serial interface ...................................... 1 port (8-bit clock synchronous system) l lcd driver ............................................. 60 segments 8 / 16 / 17 commons ( * 1) l time base counter ................................ built-in (clock timer, stopwatch timer) l programmable timer ............................. built-in (8 bits 2 ch., with event counter function) l watchdog timer ..................................... built-in l sound generator ................................... with envelope and 1-shot output functions l interrupts ............................................... external : input port interrupt 2 lines internal : clock timer interrupt 4 lines stopwatch timer interrupt 2 lines programmable timer interrupt 2 lines serial interface interrupt 1 line l supply voltage ...................................... 2.7 to 5.5v l operating temperature .......................... -20 to 70c l evaluation chip with flash built-in l compatible with e0c63454, 458 and 466 l on-board writing supported wide voltage operation products
2 E0C63P466 l current consumption (typ.) .................. single clock (osc1: crystal oscillation) halt mode (32khz) 3v 10% 2a ( * 2) 5v 10% 2a ( * 2) operating mode (32khz) 3v 10% 300a 5v 10% 1ma twin clock operating mode (4mhz) 3v 10% 2ma 5v 10% 4ma l package ................................................ qfp8-144pin / qfp17-144pin ( * 3, * 4) or die form * 1: can be selected with software * 2: target current (this value has possibility to change.) * 3: 128-pin package is not available * 4: parallel programming is supported only qfp17-144pin n block diagram osc1 osc2 osc3 osc4 v ddf vepext rstout sprg clkin txd rxd sclk com0?6 seg0?9 v dd v c1 5 ca?f v d1 v ss v ref bz svd k00?03 k10?13 test reset p00?03 p10?13 p20?23 r00?03 r10?13 r20?23 core cpu e0c63000 prom 16,384 words 13 bits prom programmer system reset control interrupt generator osc ram 5,120 words 4 bits data prom 4,096 words 4 bits lcd driver 60 seg 17 com power controller svd sound generator stopwatch timer clock timer programmable timer/counter input port serial interface i/o port output port
3 E0C63P466 n prom programming and operating mode the E0C63P466 has built-in flash eeproms as the instruction rom and the data rom that allow the developer to program the rom data using the exclusive prom writer (universal rom writer ii). this section ex- plains the prom programmer that controls data writing and the writing mode. l configuration of prom programmer the configuration of the prom programmer is shown below. serial interface controller instruction prom programming control circuit parallel interface controller v ddf v ss rxd txd sclk clkin address data control signal sprg data prom prom programmer prom block from/to exclusive prom writer the prom programmer supports the following two writing modes. 1) serial programming 2) parallel programming (only qfp17-144pin) serial programming mode uses the serial communication ports of the prom writer and E0C63P466 to write data. this mode enables on-board programming by designing the target board with a serial writing function. in parallel programming mode, the on-chip flash rom can be directly programmed using the exclusive prom writer with the adaptor socket installed. refer to "operating mode" for each programming method. terminals the E0C63P466 provides the following terminals for programming the flash eeprom. v ddf power supply (+) terminal for flash eeprom sprg flash programming control terminal (pull-up resistor built-in) when set to high normal operation mode (the cpu executes the program in the flash eeprom.) when set to low programming mode (for writing data to the flash eeprom) sclk serial transfer clock input/output terminal for serial programming (pull-up resistor built-in) rxd serial data input terminal for serial programming (pull-up resistor built-in) txd serial data output terminal for serial programming clkin prom programmer clock input terminal (1mhz; pull-up resistor built-in) rstout test signal monitor terminal (not used when writing; keep it open) vepext test signal monitor terminal (not used when writing; keep it open) the eight terminals above are provided exclusively for the flash eeprom. the e0c63454, e0c63458 and e0c63466 do not have these terminals.
4 E0C63P466 l operating mode three operating modes are available in the E0C63P466: one is for normal operation and the others are for programming. the operating mode is decided by the terminal settings at power-on or initial reset. when the sprg terminal is set to low, the E0C63P466 enters serial programming mode. to operate the E0C63P466 in normal operation mode (to execute the instruction written to the flash eeprom after program- ming), the sprg terminal should be set to high or open. the parallel programming including the mode switching and terminal settings is controlled by the exclusive prom writer. the following table lists the operating modes. operating mode normal operation mode serial programming mode parallel programming mode sprg terminal high or open low set by the prom writer normal operation mode in this mode, the e0c63000 core cpu and the peripheral circuits operate by the instructions programmed in the flash eeprom. the flash eeprom bit data is set to "1" at shipment. in normal operation mode, set the terminals for programming the flash eeprom as below. the board must be designed so that the terminal settings cannot be changed while the ic is operating. terminal v ddf sprg sclk rxd txd clkin rstout vepext set-up supply the same voltage as v dd high or open high or open high or open open high or open open open serial programming mode serial programming mode writes data to the flash eeprom using a serial communication between the exclu- sive prom writer (universal rom writer ii) and the E0C63P466. by providing a serial communication port on the target board, the E0C63P466 on the board can be programmed (on-board writing). terminal v ddf sprg sclk rxd txd clkin rstout vepext set-up supply the same voltage as v dd low connected to the prom writer connected to the prom writer connected to the prom writer connected to the prom writer open open when the sprg terminal is set to low, the E0C63P466 starts operating in serial programming mode after power-on or an initial reset. be sure not to change the sprg terminal status during normal operation or serial programming, because the operating mode may change according to the terminal status. the serial programming is performed using the 1mhz clock supplied from the prom writer to the clkin termi- nal. take noise measure into consideration so that noise does not affect the clock line input to the clkin terminal when designing the target board.
5 E0C63P466 the prom writer does not supply the source voltage to the E0C63P466 during serial programming. therefore, supply a 5v source voltage between the v dd and v ss terminals and between the v ddf and v ss terminals of the E0C63P466. furthermore, to start a serial programming, an initial reset to the E0C63P466 is required. use the reset terminal to reset the E0C63P466 securely. parallel programming mode the parallel programming can be performed by installing the E0C63P466 to the exclusive prom writer via the adaptor socket. in this mode, it is not necessary to set up the programming terminals since it is controlled by the exclusive prom writer. for the E0C63P466, the adaptor socket for the qfp17-144pin package only is available. note that the qfp8-144pin and qfp5-128pin packages are not supported. package type qfp17-144pin qfp8-144pin qfp5-128pin adapter socket support available not available not available when using a package other than qfp17-144pin or a die form, perform on-board programming in serial pro- gramming mode.
6 E0C63P466 n differences from the mask rom models this section explains the differences in functions (except for the flash eeprom block) between the E0C63P466 and the mask rom models (e0c63454, e0c63458 and e0c63466). l mask option the mask option items are fixed in the E0C63P466 as shown in the table below. mask option osc1 oscillation circuit osc3 oscillation circuit multiple key entry reset combination multiple key entry reset time authorization input port pull-up resistor k00 k01 k02 k03 k10 k11 k12 k13 output port specification r00 r01 r02 r03 r1x r2x i/o port specification p0x p1x p20 p21 p22 p23 i/o port pull-up resistor p0x p1x p20 p21 p22 p23 lcd drive power serial interface polarity svd circuit external voltage detection sound generator buzzer output specification setting crystal oscillation (32.768 khz) use or not use not use not use with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor complementary complementary complementary complementary complementary complementary complementary complementary complementary complementary complementary complementary with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor internal power supply negative polarity use positive polarity l power supply since the E0C63P466 is produced using the flash eeprom process, the characteristics are different from those of the mask rom models. 1) operating voltage range E0C63P466: 2.7 to 5.5v e0c63454: 2.2 to 5.5v (min. 1.8v when the osc3 is not used) e0c63458: 2.2 to 5.5v (min. 1.8v when the osc3 is not used) e0c63466: 2.2 to 5.5v (min. 1.8v when the osc3 is not used)
7 E0C63P466 the circuit blocks of the E0C63P466 except for the osc1 oscillation circuit and lcd driver (cpu, rom, ram and peripheral digital circuits) operate with the source voltage supplied between the v dd and v ss terminals. therefore, the vdc register (i/o memory address: ff00h, data bit: d0) is invalidated and is used as a gen- eral-purpose register. writing "1" or "0" to this register does not affect the v d1 output voltage level. address comment d3 d2 register d1 d0 name init 1 0 ff00h clkchg oscc 0 vdc r r/w r/w clkchg oscc 0 vdc 0 0 0 osc3 on 1 osc1 off 0 cpu clock switch osc3 oscillation on/off unused general-purpose register E0C63P466 address comment d3 d2 register d1 d0 name init 1 0 ff00h clkchg oscc 0 vdc r r/w r/w clkchg oscc 0 vdc 0 0 0 osc3 on 2.1 v osc1 off 1.3 v cpu clock switch osc3 oscillation on/off unused cpu operating voltage switch (1.3 v: osc1, 2.1 v: osc3) e0c63454, e0c63458, e0c63466 2) power supply terminal for the flash eeprom (v ddf ) the E0C63P466 has a power supply (+) terminal exclusively for use with the flash eeprom block (v ddf ). in serial programming mode or normal operation mode, the v ddf terminal should be connected to the v dd terminal so that the v dd voltage level is supplied to the v ddf terminal. 3) power supply terminal for the osc1 oscillation circuit (v d1 ) the v d1 voltage that is generated by the internal voltage regulator is used only for the osc1 oscillation circuit to stabilize the oscillation. as explained in item 1 above, the vdc register (ff00h?d0) does not affect the v d1 output voltage. in the E0C63P466, the v d1 voltage is fixed as follows: v d1 output voltage = 1.6 v 0.3 v 4) power supply for driving the lcd (v c1 to v c5 ) the lcd system voltage circuit in the E0C63P466 generates the four voltages (for 1/4 bias): v c1 , v c2 , v c4 and v c5 . as similar to the e0c63454, e0c63458 and e0c63466, v c1 or v c2 is generated by the internal voltage regulator and the other three voltages are generated by boosting and reducing it. the following table lists the voltage values. lcd drive voltage v c1 (0.975?.2v) v c2 (1.950?.4v) v c4 (2.925?.6v) v c5 (3.900?.8v) v c1 standard v c1 (regulated voltage) 2 v c1 3 v c1 4 v c1 v c2 standard 1/2 v c2 v c2 (regulated voltage) 3/2 v c2 2 v c2 (v dd = 2.7 to 5.5v) since the minimum operating voltage of the E0C63P466 is 2.7v, either v c1 standard or v c2 standard can be selected. v c2 standard can improve the display quality and reduce current consumption. however, in the mask rom model, v c1 standard must be selected when using the ic with a 2.6v or less operating voltage v dd . take this into consideration when creating a program.
8 E0C63P466 l rom, ram the E0C63P466 employs a flash eeprom for the internal rom. the flash eeprom can be rewritten up to 10 times. rewriting data is done at the user's own risk. the following table lists the internal memory size of each model. memory code rom data ram data rom display ram E0C63P466 16k 13 bits 5,120 4 bits 2k 4 bits 1,020 4 bits e0c63454 4k 13 bits 1,024 4 bits 2k 4 bits 680 4 bits e0c63458 8k 13 bits 5,120 4 bits 2k 4 bits 1,020 4 bits e0c63466 16k 13 bits 1,792 4 bits 2k 4 bits 1,020 4 bits the code rom and data rom of the E0C63P466 is a flash eeprom and can be rewritten using the exclusive prom writer. the size is set according to the largest model among the e0c63454, e0c63458 and e0c63466. when developing an application for the e0c634xx series mask rom model, pay attention to the memory size. l input/output ports and lcd driver the configuration of the input/output ports and lcd driver is the same as those of the e0c63466. the following table lists the configuration of each model. port input (k) port output (r) port i/o (p) port lcd driver E0C63P466 8 bits 12 bits 12 bits 60 seg 17 com e0c63454 4 bits 4 bits 8 bits 40 seg 17 com e0c63458 8 bits 12 bits 12 bits 60 seg 17 com e0c63466 8 bits 12 bits 12 bits 60 seg 17 com note that the e0c63454 supports only one system of the external input interrupt since the input port is configured with 4 bits (k00Ck03). refer to the "e0c63454 technical manual" for details. l oscillation circuit the E0C63P466 has two oscillation circuits built-in: osc1 generates a low-speed clock and osc3 generates a high-speed clock. in the e0c63454, e0c63458 and e0c63466, the osc1 and osc3 oscillation circuits operate with the internal regulated voltage v d1 , note, however, the osc3 oscillation circuit in the E0C63P466 operates with the supply voltage v dd . therefore, the oscillation characteristics of the E0C63P466 are different from those of the mask rom model (e0c634xx). when using the E0C63P466 as a development tool for the mask rom model, the constant of the osc3 oscillation circuit must be decided according to the characteristics of the mask rom model. also the osc1 oscillation circuit of the E0C63P466 has differences in its production process from the mask rom models. the constant must be decided according to the characteristics of the mask rom model. the following table lists the configuration of the oscillation circuits for each model. oscillation circuit osc1 osc3 E0C63P466 32.768khz crystal 4.1mhz (max.) ceramic e0c63454 32.768khz crystal 60khz (typ.) cr 1.8mhz (typ.) cr 4.1mhz (max.) ceramic e0c63458 32.768khz crystal 60khz (typ.) cr 1.8mhz (typ.) cr 4.1mhz (max.) ceramic e0c63466 32.768khz crystal 60khz (typ.) cr 1.8mhz (typ.) cr 4.1mhz (max.) ceramic * in the mask rom models, either crystal or cr can be selected for the osc1 oscillation circuit by mask option and either cr or ceramic can be selected for the osc3 oscillation circuit.
9 E0C63P466 l svd circuit the E0C63P466 has a built-in svd (supply voltage detection) circuit with the same configuration as that of the mask rom model (e0c634xx). however, the mask option is fixed at "with external voltage detection". the following table lists the criteria voltages. svds3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 svds0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 svds1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 svds2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 E0C63P466 1.05 (external voltage) 2.80 2.90 3.00 3.10 3.20 3.30 e0c634xx 1.85/1.05 1.90 2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.30 criteria voltage (v) a criteria voltage can be set using the svds0Csvds3 register (i/o memory address: ff04h). since the minimum operating voltage of the E0C63P466 is 2.7v, 2.7v or less criteria voltages are not available. be aware that the svd circuit in the E0C63P466 may not operate when a 2.7v or less criteria voltage is selected. for the software control sequence of the svd circuit, refer to the "e0c634xx technical manual".
10 E0C63P466 n electrical characteristics l absolute maximum ratings rating supply voltage prom power voltage input voltage (1) input voltage (2) permissible total output current * 1 operating temperature storage temperature soldering temperature / time permissible dissipation * 2 * 1: * 2: the permissible total output current is the sum total of the current (average current) that simultaneously flows from the outpu t pins (or is draw in). in case of plastic package (qfp8-144pin, qfp17-144pin). symbol v dd v ddf v i v iosc s i vdd topr tstg tsol p d value -0.5 to 7.0 -0.5 to 7.0 -0.5 to v dd + 0.3 -0.5 to v dd + 0.3 10 -20 to 70 -65 to 150 260 c, 10sec (lead section) 250 unit v v v v ma c c mw (v ss =0v) l recommended operating conditions condition supply voltage prom power voltage oscillation frequency svd terminal input voltage symbol v dd v ddf f osc1 f osc3 svd remark v ss =0v normal operation mode programming mode crystal oscillation ceramic oscillation v svd v dd , criteria voltage=1.05v unit v v v khz mhz v (ta=-20 to 70 c) max. 5.5 5.5 5.5 4.1 5.5 typ. 5.0 32.768 min. 2.7 2.7 4.5 0 l dc characteristics unit v v v v a a a ma ma ma ma a a a a (unless otherwise specified: v dd =3.0v, v ss =0v, f osc1 =32.768khz, ta=25 c, v d1 /v c1 /v c2 /v c4 /v c5 are internal voltage, c 1 ? 8 =0.2 f) max. v dd v dd 0.2? d 0.1? dd 0.5 0 -6 -2 -2 -25 -10 typ. min. 0.8? dd 0.9? dd 0 0 0 -0.5 -16 3 3 25 10 characteristic high level input voltage (1) high level input voltage (2) low level input voltage (1) low level input voltage (2) high level input current low level input current (1) low level input current (2) high level output current (1) high level output current (2) low level output current (1) low level output current (2) common output current segment output current symbol v ih1 v ih2 v il1 v il2 i ih i il1 i il2 i oh1 i oh2 i ol1 i ol2 i oh3 i ol3 i oh4 i ol4 v ih =3.0v v il1 =v ss no pull-up v il2 =v ss with pull-up v oh1 =0.9? dd v oh2 =0.9? dd v ol1 =0.1? dd v ol2 =0.1? dd v oh3 =v c5 -0.05v v ol3 =v ss +0.05v v oh4 =v c5 -0.05v v ol4 =v ss +0.05v condition k00?3, k10?3 p00?3, p10?3, p20?3 reset, test k00?3, k10?3 p00?3, p10?3, p20?3 reset, test k00?3, k10?3 p00?3, p10?3, p20?3 reset, test k00?3, k10?3 p00?3, p10?3, p20?3 reset, test k00?3, k10?3 p00?3, p10?3, p20?3 reset, test r00?3, r10?3, r20?3 p00?3, p10?3, p20?3 bz r00?3, r10?3, r20?3 p00?3, p10?3, p20?3 bz com0?om16 seg0?eg59
11 E0C63P466 unit v v v v a a a ma ma ma ma a a a a (unless otherwise specified: v dd =5.0v, v ss =0v, f osc1 =32.768khz, ta=25 c, v d1 /v c1 /v c2 /v c4 /v c5 are internal voltage, c 1 ? 8 =0.2 f) max. v dd v dd 0.2? d 0.1? dd 0.5 0 -10 -5 -5 -25 -10 typ. -15 min. 0.8? dd 0.9? dd 0 0 0 -0.5 -25 7.5 7.5 25 10 characteristic high level input voltage (1) high level input voltage (2) low level input voltage (1) low level input voltage (2) high level input current low level input current (1) low level input current (2) high level output current (1) high level output current (2) low level output current (1) low level output current (2) common output current segment output current symbol v ih1 v ih2 v il1 v il2 i ih i il1 i il2 i oh1 i oh2 i ol1 i ol2 i oh3 i ol3 i oh4 i ol4 v ih =5.0v v il1 =v ss no pull-up v il2 =v ss with pull-up v oh1 =0.9? dd v oh2 =0.9? dd v ol1 =0.1? dd v ol2 =0.1? dd v oh3 =v c5 -0.05v v ol3 =v ss +0.05v v oh4 =v c5 -0.05v v ol4 =v ss +0.05v condition k00?3, k10?3 p00?3, p10?3, p20?3 reset, test k00?3, k10?3 p00?3, p10?3, p20?3 reset, test k00?3, k10?3 p00?3, p10?3, p20?3 reset, test k00?3, k10?3 p00?3, p10?3, p20?3 reset, test k00?3, k10?3 p00?3, p10?3, p20?3 reset, test r00?3, r10?3, r20?3 p00?3, p10?3, p20?3 bz r00?3, r10?3, r20?3 p00?3, p10?3, p20?3 bz com0?om16 seg0?eg59 l analog circuit characteristics unit v v v v (unless otherwise specified: v dd =3.0v, v ss =0v, f osc1 =32.768khz, c g =25pf, ta=25 c, v d1 /v c1 /v c2 /v c4 /v c5 are internal voltage, c 1 ? 8 =0.2 f) max. typ. 1.12 2? c1 0.9 3? c1 0.9 4? c1 0.9 typ. 0.975 0.990 1.005 1.020 1.035 1.050 1.065 1.080 1.095 1.110 1.125 1.140 1.155 1.170 1.185 1.200 min. typ. 0.88 2? c1 3? c1 4? c1 characteristic lcd drive voltage (when v c1 standard is selected) symbol v c1 v c2 v c4 v c5 condition connect 1m w load resistor between v ss and v c1 (no panel load) connect 1m w load resistor between v ss and v c2 (no panel load) connect 1m w load resistor between v ss and v c4 (no panel load) connect 1m w load resistor between v ss and v c5 (no panel load) lc0?="0" lc0?="1" lc0?="2" lc0?="3" lc0?="4" lc0?="5" lc0?="6" lc0?="7" lc0?="8" lc0?="9" lc0?="a" lc0?="b" lc0?="c" lc0?="d" lc0?="e" lc0?="f"
12 E0C63P466 unit v v v v v v s a a a a ma ma ma (unless otherwise specified: v dd =3.0v, v ss =0v, f osc1 =32.768khz, c g =25pf, ta=25 c, v d1 /v c1 /v c2 /v c4 /v c5 are internal voltage, c 1 ? 8 =0.2 f) max. 1/2? c2 0.95 typ. 1.12 3/2? c2 2? c2 1.15 typ. 1.02 100 5 19 15 typ. 1.95 1.98 2.01 2.04 2.07 2.10 2.13 2.16 2.19 2.22 2.25 2.28 2.31 2.34 2.37 2.40 1.05 2.80 2.90 3.00 3.10 3.20 3.30 2 11 9 300 1 2 4 min. 1/2? c2 -0.1 typ. 0.88 3/2? c2 0.95 2? c2 0.95 0.95 typ. 0.93 characteristic lcd drive voltage (when v c2 standard is selected) svd voltage svd circuit response time current consumption symbol v c1 v c2 v c4 v c5 v svd1 t svd i op condition connect 1m w load resistor between v ss and v c1 (no panel load) connect 1m w load resistor between v ss and v c2 (no panel load) connect 1m w load resistor between v ss and v c4 (no panel load) connect 1m w load resistor between v ss and v c5 (no panel load) svds0?="0" (external) * 3 svds0?="1" svds0?="2" svds0?="3" svds0?="4" svds0?="5" svds0?="6" svds0?="7" svds0?="8" svds0?="9" svds0?="10" svds0?="11" svds0?="12" svds0?="13" svds0?="14" svds0?="15" during halt (32khz, crystal) during execution (32khz, crystal) during execution (4mhz, ceramic) lc0?="0" lc0?="1" lc0?="2" lc0?="3" lc0?="4" lc0?="5" lc0?="6" lc0?="7" lc0?="8" lc0?="9" lc0?="a" lc0?="b" lc0?="c" lc0?="d" lc0?="e" lc0?="f" * 1: * 2: * 3: * 4: no panel load. the svd circuit is off. oscc="0" do not apply a voltage level that exceeds the v ss ? dd range to the svd terminal. target current (this value has possibility to change.) lcd power off * 1, * 2, * 4 lcd power on (v c1 standard) * 1, * 2 lcd power on (v c2 standard) * 1, * 2 v dd =3.0v * 1, * 2 v dd =5.0v * 1, * 2 v dd =3.0v * 1 v dd =5.0v * 1
13 E0C63P466 n package l package dimensions 28 ?.1 31.2 ?.4 73 108 28 ?.1 31.2 ?.4 37 72 index 0.3 ?.1 36 1 144 109 3.35 ?.1 0.1 3.65 max 0.6 ?.2 0 10 0.15 ?.05 0.65 1.6 20 ?.1 22 ?.4 73 108 20 ?.1 22 ?.4 37 72 index 0.2 36 1 144 109 2.7 ?.1 0.1 3 max 0.5 ?.2 0 10 0.15 ?.05 0.5 1 +0.1 ?.05 plastic qfp8-144pin plastic qfp17-144pin unit: mm l pin layout the dimensions are subject to change without notice. no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 e0c63458 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 com7 com6 com5 com4 n.c. com3 com2 com1 com0 bz v ss osc1 osc2 v d1 osc3 osc4 v dd reset test v ref n.c. n.c. e0c63466 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 com7 com6 com5 com4 n.c. com3 com2 com1 com0 bz v ss osc1 osc2 v d1 osc3 osc4 v dd reset test v ref n.c. n.c. E0C63P466 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 com7 com6 com5 com4 n.c. com3 com2 com1 com0 bz v ss osc1 osc2 v d1 osc3 osc4 v dd reset test v ref clkin sclk pin name no. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 e0c63458 n.c. n.c. r23 r22 r21 r20 r13 r12 r11 r10 r03 r02 r01 r00 p23 p22 p21 p20 p13 p12 p11 p10 p03 p02 p01 p00 k13 k12 k11 k10 k03 k02 k01 k00 n.c. n.c. e0c63466 n.c. n.c. r23 r22 r21 r20 r13 r12 r11 r10 r03 r02 r01 r00 p23 p22 p21 p20 p13 p12 p11 p10 p03 p02 p01 p00 k13 k12 k11 k10 k03 k02 k01 k00 n.c. n.c. E0C63P466 rxd txd r23 r22 r21 r20 r13 r12 r11 r10 r03 r02 r01 r00 p23 p22 p21 p20 p13 p12 p11 p10 p03 p02 p01 p00 k13 k12 k11 k10 k03 k02 k01 k00 sprg n.c. pin name no. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 e0c63458 n.c. svd v c1 v c2 v c3 v c4 v c5 cf ce cd cc cb ca com8 com9 com10 com11 com12 com13 com14 com15 com16 seg59 seg58 seg57 seg56 seg55 seg54 seg53 seg52 seg51 seg50 seg49 seg48 n.c. n.c. e0c63466 n.c. svd v c1 v c2 v c3 v c4 v c5 cf ce cd cc cb ca com8 com9 com10 com11 com12 com13 com14 com15 com16 seg59 seg58 seg57 seg56 seg55 seg54 seg53 seg52 seg51 seg50 seg49 seg48 n.c. n.c. E0C63P466 v ddf svd v c1 v c2 v c3 v c4 v c5 cf ce cd cc cb ca com8 com9 com10 com11 com12 com13 com14 com15 com16 seg59 seg58 seg57 seg56 seg55 seg54 seg53 seg52 seg51 seg50 seg49 seg48 vepext n.c. pin name no. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 e0c63458 n.c. seg47 seg46 seg45 seg44 seg43 seg42 seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 n.c. e0c63466 n.c. seg47 seg46 seg45 seg44 seg43 seg42 seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 n.c. E0C63P466 rstout seg47 seg46 seg45 seg44 seg43 seg42 seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 n.c. pin name
14 E0C63P466 n pad layout l diagram of pad layout pad opening: 95 m l pad coordinates no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 name rxd txd r23 r22 r21 r20 r13 r12 r11 r10 r03 r02 r01 r00 p23 p22 p21 p20 p13 p12 p11 p10 p03 p02 p01 p00 k13 k12 k11 k10 k03 k02 k01 k00 sprg x ( m) 2,226 2,081 1,935 1,805 1,674 1,544 1,428 1,313 1,197 1,082 966 851 735 620 497 381 266 150 35 -81 -197 -312 -428 -543 -659 -774 -897 -1,013 -1,128 -1,244 -1,374 -1,505 -1,635 -1,781 -1,926 y ( m) 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 no. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 name v ddf svd v c1 v c2 v c3 v c4 v c5 cf ce cd cc cb ca com8 com9 com10 com11 com12 com13 com14 com15 com16 seg59 seg58 seg57 seg56 seg55 seg54 seg53 seg52 seg51 seg50 seg49 seg48 vepext x ( m) -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 y ( m) 2,256 2,111 1,965 1,820 1,689 1,559 1,428 1,313 1,197 1,082 966 851 735 612 497 381 266 150 35 -81 -197 -312 -443 -558 -674 -789 -905 -1,020 -1,136 -1,266 -1,397 -1,527 -1,673 -1,818 -1,964 no. 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 name rstout seg47 seg46 seg45 seg44 seg43 seg42 seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 x ( m) -2,318 -2,187 -2,051 -1,936 -1,809 -1,694 -1,567 -1,452 -1,325 -1,210 -1,083 -968 -841 -725 -599 -483 -357 -241 -115 1 128 243 370 485 612 727 854 969 1,096 1,211 1,338 1,454 1,580 1,711 1,852 y ( m) -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 -2,537 no. 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 name seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 com7 com6 com5 com4 com3 com2 com1 com0 bz v ss osc1 osc2 v d1 osc3 osc4 v dd reset test v ref clkin sclk x ( m) 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 2,537 y ( m) -2,181 -2,039 -1,909 -1,767 -1,637 -1,510 -1,395 -1,268 -1,153 -1,026 -911 -784 -668 -542 -419 -303 -188 -72 58 174 289 405 535 651 766 882 997 1,113 1,228 1,359 1,489 1,620 1,765 1,911 2,056 x y (0, 0) 5.30 mm 5.30 mm die no. 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 140
15 E0C63P466 n pin description pin name v dd v ss v d1 v c1 ? c5 v ref ca?f osc1 osc2 osc3 osc4 k00?03 k10?12 k13 p00?03 p10?13 p20 p21 p22 p23 r00 r01 r02 r03 r10?13 r20?23 com0?om16 seg0?eg59 bz svd reset test txd rxd sclk clkin sprg rstout v ddf vepext function power (+) supply pin power (? supply pin oscillation/internal logic system regulated voltage output pin lcd system power supply pin lcd system power supply testing pin lcd system boosting capacitor connecting pin crystal oscillation input pin crystal oscillation output pin ceramic oscillation input pin ceramic oscillation output pin input pin input pin input pin (can be used as external clock input pin for event counter) i/o pin i/o pin (switching to serial i/f input/output is possible by software) i/o pin i/o pin i/o pin (switching to cl signal output is possible by software) i/o pin (switching to fr signal output is possible by software) output pin output pin output pin (switching to tout signal output is possible by software) output pin (switching to fout signal output is possible by software) output pin output pin lcd common output pin (1/8, 1/16, 1/17 duty can be selected by software) lcd segment output pin sound output pin svd external voltage input pin initial reset input pin testing input pin serial data output pin for flash programming serial data input pin for flash programming serial clock i/o pin for flash programming clock input pin for flash programming testing input pin for flash programming flash testing pin (leave it open during normal operation) flash power (+) supply pin (normally connect to v dd pin) flash testing pin (leave it open during normal operation) pin no. 31 25 28 75?9 34 85?0 26 27 29 30 70?7 66?4 63 62?9 58?5 54 53 52 51 50 49 48 47 46?3 42?9 23?0, 18?5 86?4 14? 143?10 106?5 24 74 32 33 38 37 36 35 71 109 73 107 pad no. 135 129 132 38?2 138 48?3 130 131 133 134 34?1 30?8 27 26?3 22?9 18 17 16 15 14 13 12 11 10? 6? 127?20 49?7 119?2 69?8 128 37 136 137 2 1 140 139 35 71 36 70 i/o o i o i o i i i i/o i/o i/o i/o i/o i/o o o o o o o o o o i i i o i i/o i i o i/o
E0C63P466 notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is n o representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to an y intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accord ance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 2000 all right reserved. seiko epson corporation electronic devices marketing division ic marketing & engineering group ed international marketing department i (europe & u.s.a.) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5812 fax : 042-587-5564 ed international marketing department ii (asia) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5814 fax : 042-587-5110 http://www.epson.co.jp/device/ n epson electronic devices website

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